1. Field of the Invention
The embodiments of the invention generally relate to complementary metal oxide semiconductor (CMOS) device fabrication, and more particularly to a method of forming self-aligned dual fully silicided (FUSI) gates in CMOS technologies to improve device performance.
2. Description of the Related Art
A polysilicon gate is commonly used in CMOS technology. Polysilicon gates have polysilicon depletion that effectively increases the equivalent gate dielectric thickness, thus degrading device performance. Fully silicided (FUSI) gates eliminate the problem of polysilicon depletion. FUSI gates also reduce the gate conductance that can further improve device performance. A FUSI gate can be formed by depositing a metal layer (such as Ti, Co, Ni, etc.) over an exposed polysilicon gate region, and then annealing the semiconductor structure. The metal reacts with the exposed polysilicon gate to transform the polysilicon gate fully into a silicided gate. FUSI gates normally have a work function near the middle of the silicon band structure. However, CMOS devices normally require a conductive gate with a work function near the band edge; i.e., near the conduction band for an NFET and near the valence band for a PFET, respectively. This imposes a significant challenge for CMOS technologies with FUSI gates, since it likely requires different FUSI gates to be formed for each of the NFET and PFET portions of the CMOS device.
FIGS. 1 through 4 illustrate iterative steps of a conventional method to form a CMOS device 51 with dual fully silicided gate (i.e., a CMOS device 51 formed of two different fully silicided gate materials for the NFET and PFET). FIG. 1 illustrates a starting CMOS device structure 51 with exposed polysilicon gates 58, 63 for the NFET 80 and PFET 70, respectively. The CMOS device 51 consists of a substrate 52 with Nwell (N-type retrograde well) and Pwell (P-type retrograde well) regions 53, 54, respectively configured therein. Shallow trench isolation regions 55 are also included in the CMOS device 51. The NFET portion 80 of the CMOS device 51 comprises a NFET gate 58. Additionally, insulative sidewall spacers 59 are configured around the NFET gate 58. A NFET gate dielectric 57 is positioned below the NFET gate 58. Moreover, NFET source/drain implant regions 68 comprising NFET source/drain silicide areas 56 are also formed in the Pwell region 54 on opposite sides of the NFET gate 58.
Likewise, the PFET portion 70 of the CMOS device 51 comprises a PFET gate 63. Additionally, insulative sidewall spacers 61 are configured around the PFET gate 63. A PFET gate dielectric 62 is positioned below the PFET gate 63. Additionally, PFET source/drain implant regions 69 comprising PFET source/drain silicide areas 66 are also formed in the Nwell region 53 on opposite sides of the PFET gate 63. Furthermore, a dielectric film 60 is formed planar with the NFET and PFET gates 58, 63 and above the NFET and PFET source/drain silicide areas 56, 66.
Generally, as illustrated in FIG. 2, the dual FUSI gate process involves depositing a first silicide block film 65 over the entire device 51. Then, a first lithographic pattern and etching process is performed to remove a portion of the blocking film 65 over the NFET region 80 of the device 51. A silicide process is performed on the NFET gate 58 to form a fully silicided gate region 158.
Next, as shown in FIG. 3, the first blocking film 65 is removed from the device 51, and a second silicide blocking film 67 is deposited over the entire device 51. Then, a second lithographic pattern and etching process is performed to remove a portion of the blocking film 67 over the PFET region 70 of the device 51. Thereafter, a silicide process is performed on the PFET gate region 63 to form a FUSI gate 163. As shown in FIG. 4, the second blocking film 67 is completely removed. Additionally, as indicated in FIG. 4, the material of the NFET FUSI gate 158 is different from the material of the PFET FUSI gate 163 of the device 51.
However, one of the problems with the conventional two lithography level dual FUSI gate process as provided in FIGS. 1 through 4 is the misalignment caused during the processing between the two lithography levels as illustrated in FIG. 5 (the dotted circle represents the area of the device 51 where the misalignment occurs). This misalignment between the NFET FUSI gate 158 of the NFET region 80 and the PFET FUSI gate 163 of the PFET region 70 results in an underlay in the device 51 (illustrated in FIG. 5 as a SRAM (synchronous random access memory) cell layout), which can cause high sheet resistance or an open circuit in the device and/or circuit areas thereby resulting in inferior device/circuit performance. Therefore, there remains a need for a novel dual FUSI gate formation process, which overcomes this misalignment problem.